This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding system failures.
Personal computer systems in general and IBM personal computers in particular have attained widespread use for providing computer power to many segments of today's modern society. Personal computer systems can usually be defined as a desk top, floor standing, or portable microcomputer that consists of a system unit having a single system processor and associated volatile and non-volatile memory, a display monitor, a keyboard, one or more diskette drives, a fixed disk storage, and an optional printer. One of the distinguishing characteristics of these systems is the use of a motherboard or system planar to connect these components together. These systems are designed primarily to give independent computing power to a single user and are inexpensively priced for purchase by individuals or small businesses. Examples of such personal computer systems are IBM's PERSONAL COMPUTER AT and IBM's PERSONAL SYSTEM/2 Models 25, 30, L40SX, 50, 55, 65, 70, 80, 90 and 95.
These systems can be classified into two general families. The first family, usually referred to as Family I Models, use a bus architecture exemplified by the IBM PERSONAL COMPUTER AT and other "IBM compatible" machines. The second family, referred to as Family II Models, use IBM's MICRO CHANNEL bus architecture exemplified by IBM's PERSONAL SYSTEM/2 Models 50 through 95. In the beginning, the Family I models typically used the popular INTEL 8088 or 8086 microprocessor as the system processor. These processors have the ability to address one megabyte of memory. Later Family I models and the Family II models typically use the higher speed INTEL 80286, 80386, and 80486 microprocessors which can operate in a real mode to emulate the slower speed INTEL 8086 microprocessor or a protected mode which extends the addressing range from 1 megabyte to 4 Gigabytes for some models. In essence, the real mode feature of the 80286, 80386, and 80486 processors provide hardware compatibility with software written for the 8086 and 8088 microprocessors.
In all such personal computers using INTEL X86 microprocessors, the microprocessor serving as the system CPU may be reset by an appropriate RESET signal, issued on initial power-up of the system or under certain operating conditions (and in the latter instance sometimes known as a HOTRESET signal). Reset of an X86 processor terminates any operation in progress and returns the processor to a known state. Abnormal termination of a cycle in progress can give rise to failures in operation of the computer system for several different reasons. This is particularly true where the computer system is an advanced system such as one of the Family II systems described above. For example, if a RESET signal is received by a microprocessor while the microprocessor has also received a HOLD signal, then the microprocessor's responding hold acknowledge signal (HLDA) may be dropped or lost, upsetting the normal flow of processing by the system. Similarly, receipt of a HOLD during a reset interval triggered by a RESET may get an early HLDA which would then be lost having the same effect as the first error mentioned above. A RESET received during an active bus cycle may cause truncation of the bus cycle, again causing system errors such as leaving a slave device in an unrecoverable state. Finally, if the system involved is one which accommodates alternate masters on the local processor bus, then receipt of a RESET by the default system processor (normally the CPU) will cause the processor to acquire the local bus on resetting regardless of the status of the local processor bus with regard to alternate masters.
Such problems with Intel X86 processors have been recognized heretofore. One solution has been proposed in Culley U.S. Pat. No. 4,787,031 issued 22 Nov. 1988 and assigned to Compaq Computer Corporation, where any RESET signal is required to wait until any pending microprocessor HOLD signal is serviced. However, this proposed solution still suffers from the likelihood that a HLDA signal may be lost, cycle truncation will occur, or unnecessary contention between the default master and alternate masters may leave portions of the system in an indeterminate state.